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PE4305
Product Specification
Figure 14. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
V I
Parameter/Conditions
Power supply voltage
Voltage on any DC input
Min
-0.3
-0.3
Max
4.0
V DD +
0.3
Units
V
V
N/C
1
15
C8
T ST
Storage temperature range
-65
150
°C
RF1
Data
2
3
20-lead
QFN
4x4 mm
14
13
RF2
P/S
P IN
V ESD
Input power (50 ? )
ESD voltage (Human Body
Model)
+30
500
dBm
V
Clock
LE
4
5
Exposed Solder Pad
12
11
Vss/GND
GND
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
Table 2. Pin Descriptions
Table 4. Operating Ranges
Pin No.
1
2
3
Pin Name
N/C
RF1
Data
Description
No connect. Can be connected to any
bias.
RF port (Note 1).
Serial interface data input (Note 4).
Parameter
V DD Power Supply
Voltage
I DD Power Supply
Current
Digital Input High
Min
2.7
0.7xV DD
Typ
3.0
Max
3.3
100
Units
V
μ A
V
4
Clock
Serial interface clock input.
5
6
7
LE
V DD
N/C
Latch Enable input (Note 2).
Power supply pin.
No connect. Can be connected to any
bias.
Digital Input Low
Digital Input Leakage
Input Power
0.3xV DD
1
+24
V
μ A
dBm
8
PUP2
Power-up selection bit.
Temperature range
-40
85
°C
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
V DD
GND
GND
V ss /GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS? de-
vices are immune to latch-up.
Note 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k ? resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and disable
internal negative voltage generator.
4. Place a 10 k ? resistor in series, as close to pin as possible to
avoid frequency resonance. See “Resistor on Pin 3” paragraph.
Document No. 70-0159-06 │ www.psemi.com
Switching Frequency
The PE4305 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 k ? resistor on the input to Pin 3 (see Figure 16)
will eliminate package resonance between the RF input
pin and the digital input. Specified attenuation error
versus frequency performance is dependent upon this
condition.
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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